Unification of PR Region floorplanning and Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs

Dynamic Partially Recon ̄guration (DPR) designs provide additional bene ̄ts compared to traditional FPGA application. However, due to the lack of support from automatic design tools in current design °ow, designers have to manually de ̄ne the dimensions and positions of Partially Recon ̄gurable Regions (PR Regions). The following ̄ne-grained placement for system modules is also limited because it takes the °oorplanning result as a rigid region constraint. Therefore, the manual °oorplanning is laborious and may lead to inferior ̄ne-grained placement results. In this paper, we propose to integrate PR Region °oorplanning with ̄ne-grained placement to achieve the global optimization of the whole DPR system. E®ective strategies for tuning PR Region °oorplanning and apposite analytical evaluation models are customized for DPR designs to handle the co-optimization for both PR Regions and static region. Not only practical recon ̄guration cost and speci ̄c recon ̄guration constraints for DPR system are considered, but also the congestion estimation can be relaxed by our approach. Especially, we established a two-stage stochastic optimization framework which handles di®erent objectives in di®erent optimization stages so that automated °oorplanning and global optimization can be achieved in reasonable time. Experimental results demonstrate that due to the °exibility bene ̄t from the uni ̄cation of PR Region °oorplanning and ̄ne-grained placement, our approach can improve 20.9% on critical path delay, 24% on recon ̄guration delay, 12% on congestion, and 8.7% on wire length compared to current DPR design method.